As data communication systems reach multi-gigabit per second (Gbps) rates, the task of ensuring good signal integrity, both on-chip and off-chip, becomes increasingly important. At such high-speed data rates, clock jitter becomes a signal-integrity challenge. At the system-level behavior, for example, jitter generation, amplification and cancellation must be taken into account, with noise sources introduced from either off-chip or on-chip. The term “jitter” is often defined as the short-term variations of a periodic digital signal's significant instants (i.e., periodicity) from their ideal positions in time (see, e.g., Bell Communications Research, Inc. (Bellcore), “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, TR-253-CORE,” Issue 2, Rev. 1, December 1997, the disclosure of which is incorporated by reference herein in its entirety for all purposes).
High-speed signaling (e.g., greater than about 25 Gbps wireline communications) requires low jitter receiver clock sampling to achieve low bit-error rate (BER). For instance, an analog-to-digital converter (ADC) operating at ultra-high speed (e.g., greater than about 10 giga-samples per second (GS/s)) typically suffers from inaccuracy of its sampling clock due to both static and dynamic timing errors. Conventional approaches to reduce static timing error in a data communication system, including, for example, the use of phase calibration in time-interleaving techniques, have resulted in increasing the complexity (e.g., through required additional circuitry or algorithms) and/or power consumption in the system, and are therefore undesirable. Furthermore, these calibration circuits may not be able to alleviate much of the dynamic timing errors introduced by high-frequency clock jitter.